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Cypress Semiconductor /psoc63 /PROFILE /CTL

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Interpret as CTL

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (WIN_MODE)WIN_MODE 0 (ENABLED)ENABLED

Description

Profile control

Fields

WIN_MODE

Specifies the profiling time window mode: ‘0’: Start / stop mode. The profiling time window is started when a rising edge of the start trigger signal occurs and stopped when a rising edge of the stop trigger signal occurs. In case both rising edges (of start and stop trigger signals) occur in the same cycle, the profiling time window is stopped. ‘1’: Enable mode. The profiling time window is active as long as the start ‘trigger’ signal is active. The stop trigger signal has no effect.
ENABLED

Enables the profiling block: ‘0’: Disabled. ‘1’: Enabled.

Links

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Register License

Copyright 2016-2018 Cypress Semiconductor Corporation \n Licensed under the Apache License, Version 2.0 (the “License”); you may not use this file except in compliance with the License.
You may obtain a copy of the License at \n
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and
limitations under the License.

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data